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[Other] alu.v

Description: a well written and yet small verilog hardware description language or popularly known as simply Verilog program for an Arithmetic and Logic Unit or as popularly called ALU
Platform: | Size: 1024 | Author: Atin | Hits:

[Software Engineering] lab-1-ALU-design-with-Verilog-HDL

Description: cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
Platform: | Size: 19456 | Author: 张明明 | Hits:

[Books] ALU

Description: verilog语言的运算器，包含基本的加减、移位、循环移位操作-verilog language calculator, including basic addition and subtraction, shift, rotate shift operation
Platform: | Size: 1024 | Author: Jerome | Hits:

[VHDL-FPGA-Verilog] ALU

Description: verilog编写，八位ALU，加减与或比较-verilog prepared eight ALU, subtract, or compare with
Platform: | Size: 2048 | Author: 姬成 | Hits:

[Other] alu

Description: alu,利用verilog实现+、-、*、 、移位等功能-alu achieve+,-,*, , shift functions
Platform: | Size: 1024 | Author: 孙思宇 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 32位alu模块实现加减法、逻辑运算、移位、比较和置高位立即数等功能。verilog实现。-32-bit alu module achieves functions like addition and subtraction, logical operations, shift, compare, and set a high immediate number by verilog
Platform: | Size: 907264 | Author: sherlydunn | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog 编写的 可综合的ALU单元 可执行加减与或非 5种运算-verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing
Platform: | Size: 362496 | Author: peyo | Hits:

[VHDL-FPGA-Verilog] ALU-and-Register-File

Description: ALU&Register Files(RF)之實現和其資料路徑的組合，包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
Platform: | Size: 6144 | Author: sara kuo | Hits:

[VHDL-FPGA-Verilog] ALU

Description: ALU，两种类型的verilog源代码，包括测试代码，原创。-ALU, two types of verilog source code, including test code, originality.
Platform: | Size: 5120 | Author: 项中元 | Hits:

[VHDL-FPGA-Verilog] 8-bit-ALU-with-a-Newton-Raphson-Divider

Description: 8-bit ALU with a Newton-Raphson Divider Using Verilog
Platform: | Size: 104448 | Author: webking | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog code for 8 bit alu
Platform: | Size: 442368 | Author: kumar | Hits:

[VHDL-FPGA-Verilog] ALU

Description: Verilog编写的ALU，可实现数学、移位、逻辑运算-ALU Verilog prepared, enabling mathematics, shift, logical operations
Platform: | Size: 1024 | Author: | Hits:

[Other Embeded program] alu

Description: My own arithmetic and logic unit in Verilog HDL.
Platform: | Size: 1024 | Author: Jain | Hits:

[Other] alu

Description: 用Verilog HDL编写的简单算数逻辑单元-Algorithm Logic Unit programmed by Verilog HDl
Platform: | Size: 44032 | Author: 张娜 | Hits:

[Other] ALU

Description: Verilog中的ALU设计，具备ALU的功能，十分详细。-The ALU Verilog design, with ALU functions, very detailed.
Platform: | Size: 1289216 | Author: 李志强 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: This MIPS ALU verilog code-This is MIPS ALU verilog code
Platform: | Size: 3072 | Author: Kumar | Hits:

[Other] alu

Description: 用Verilog语言中的always块实现对输入数据执行加、减、与、或和求反的功能-Using Verilog language always realize the input data block to perform addition, subtraction, AND, OR, and negated function
Platform: | Size: 1024 | Author: 坚果墙 | Hits:

[VHDL-FPGA-Verilog] ALU_4_operations

Description: unid logic aritmetic- four options
Platform: | Size: 81968 | Author: fitnowredribbon | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 算术逻辑单元,可以实现加法、减法、比较、移位、与门、或门等功能(arithmetic and logic unit)
Platform: | Size: 1024 | Author: 请问让人讨厌 | Hits:

[VHDL-FPGA-Verilog] CPU_Verilog

Description: 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
Platform: | Size: 12288 | Author: fairchildfzc | Hits:
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